assertion-design
Defines SystemVerilog Assertions for timing and protocol specifications, enhancing RTL verification through executable specifications.
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The assertion-design skill was audited on Feb 19, 2026. Our scanner tested it across 12 threat categories and found no security issues.
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Scanned on Feb 19, 2026
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Categorydevelopment
UpdatedMay 21, 2026
majiayu000/claude-skill-registry